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1/29 october 2002 M41T81 serial access rtc with alarms * contact local sales office features summary 2.0 to 5.5v clock operating voltage counters for tenths/hundredths of seconds, seconds, minutes, hours, day, date, month, year, and century automatic switch-over and deselect circuitry serial interface supports i 2 c bus (400khz protocol) programmable alarm and interrupt function (valid even during battery back-up mode) watchdog timer low operating current of 400a battery back-up not recommended for 3.0v applications (capacitor back-up only) battery or super-cap back-up operating temperature of C40 to 85c ultra-low battery supply current of 1 a figure 1. 8-pin soic package figure 2. 28-pin soic package* 8 1 so8 (m) 28 1 snaphat (sh) battery & crystal soh28 (mh)
M41T81 2/29 table of contents summary description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 logic diagram (figure 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 signal names (table 1.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 8-pin soic connections (figure 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 28-pin soic connections (figure 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 block diagram (figure 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 absolute maximum ratings (table 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 dc and ac parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 operating and ac measurement conditions (table 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 ac measurement i/o waveform (figure 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 capacitance (table 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 dc characteristics (table 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 crystal electrical characteristics (table 6.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2-wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 serial bus data transfer sequence (figure 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 acknowledgement sequence (figure 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 bus timing requirements sequence (figure 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 ac characteristics (table 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 read mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 slave address location (figure 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 read mode sequence (figure 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 alternative read mode sequence (figure 13.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 write mode sequence (figure 14.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 data retention mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 power down/up mode ac waveforms (figure 15.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 power down/up ac characteristics (table 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 power down/up trip points dc characteristics (table 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3/29 M41T81 clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 timekeeper? registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 timekeeper? register map (table 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 calibrating the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 setting alarm clock registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 alarm interrupt reset waveform (figure 16.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 back-up mode alarm waveform (figure 17.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 alarm repeat modes (table 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 square wave output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 square wave output frequency (table 12.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 century bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 output driver pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 preferred initial power-on default . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 preferred default values (table 13.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 crystal accuracy across temperature (figure 18.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 clock calibration (figure 19.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 snaphat battery/crystal table (table 15.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 package mechanical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
M41T81 4/29 summary description the M41T81 serial access timekeeper ? sram is a low power serial rtc with a built-in 32.768 khz oscillator (external crystal controlled). eight bytes of the sram (see table 10, page 16) are used for the clock/calendar function and are configured in binary coded decimal (bcd) format. an additional 12 bytes of sram provide status/ control of alarm, watchdog and square wave functions. addresses and data are transferred se- rially via a two line, bi-directional i 2 c interface. the built-in address register is incremented automati- cally after each write or read data byte. the M41T81 has a built-in power sense circuit which detects power failures and automatically switches to the battery supply when a power fail- ure occurs. the energy needed to sustain the sram and clock operations can be supplied by a small lithium button supply when a power failure occurs. functions available to the user include a non-volatile, time-of-day clock/calendar, alarm in- terrupts, watchdog timer and programmable square wave output. the eight clock address lo- cations contain the century, year, month, date, day, hour, minute, second and tenths/hundredths of a second in 24 hour bcd format. corrections for 28, 29 (leap year - valid until year 2100), 30 and 31 day months are made automatically. the M41T81 is supplied in either an 8-pin soic or a 28-lead soic snaphat ? package (which inte- grates both crystal and battery in a single snaphat top). the 28-pin, 330mil soic provides sockets with gold plated contacts at both ends for direct connection to a separate snaphat hous- ing containing the battery and crystal. the unique design allows the snaphat battery/crystal pack- age to be mounted on top of the soic package af- ter the completion of the surface mount process. insertion of the snaphat housing after reflow prevents potential battery and crystal damage due to the high temperatures required for device sur- face-mounting. the snaphat housing is also keyed to prevent reverse insertion. the soic and battery/crystal packages are shipped separately in plastic anti-static tubes or in tape & reel form. for the 28 lead soic, the bat- tery/crystal package (e.g., snaphat) part num- ber is m4txx-br12sh (see table 15, page 23). caution: do not place the snaphat battery/crys- tal top in conductive foam, as this will drain the lith- ium button-cell battery. figure 3. logic diagram note: 1. for so8 package only. table 1. signal names note: 1. for so8 package only scl v cc M41T81 v ss sda irq/ft/out/sqw v bat (1) xi (1) xo (1) ai04613 xi (1) oscillator input xo (1) oscillator output irq /out/ ft/sqw interrupt / output driver / frequency test / square wave (open drain) sda serial data input/output scl serial clock input v bat (1) battery supply voltage v cc supply voltage v ss ground
5/29 M41T81 figure 4. 8-pin soic connections figure 5. 28-pin soic connections figure 6. block diagram 2 3 45 6 8 7 1 irq/ft/out/sqw sda v bat scl v ss xo xi v cc M41T81 ai04769 8 2 3 4 5 6 7 9 10 11 12 13 14 22 21 20 19 18 17 16 15 28 27 26 25 24 23 1 nc nc nc nc nc nc nc nc irq/ft/out/sqw nc nc nc nc nc scl nc nc nc v ss sda nc nc nc v cc M41T81 nc nc nc nc ai04615 real time clock calendar rtc w/alarm & calibration watchdog square wave irq/ft/out/sqw (1) internal power wdf af sda scl v cc compare i 2 c interface 32khz oscillator v bat crystal v so (2) note 1. open drain output note 2. v so = v bat C 0.5v (typ) ai04616 write protect
M41T81 6/29 maximum rating stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicat- ed in the operating sections of this specification is not implied. exposure to absolute maximum rat- ing conditions for extended periods may affect de- vice reliability. refer also to the stmicroelectronics sure program and other rel- evant quality documents. table 2. absolute maximum ratings note: 1. reflow at peak temperature of 215c to 225c for < 60 seconds (total thermal budget not to exceed 180c for between 90 t o 120 seconds). caution : negative undershoots below C0.3 volts are not allowed on any pin while in the battery back-up mode caution : do not wave solder soic to avoid damaging snaphat socket. sym parameter value unit t stg storage temperature (v cc off, oscillator off) snaphat ? C40 to 85 c soic C55 to 125 c v cc supply voltage C0.3 to 7 v t sld (1) lead solder temperature for 10 seconds 260 c v io input or output voltages C0.3 to vcc+0.3 v i o output current 20 ma p d power dissipation 1 w
7/29 M41T81 dc and ac parameters this section summarizes the operating and mea- surement conditions, as well as the dc and ac characteristics of the device. the parameters in the following dc and ac characteristic tables are derived from tests performed under the measure- ment conditions listed in the relevant tables. de- signers should check that the operating conditions in their projects match the measurement condi- tions when using the quoted parameters. table 3. operating and ac measurement conditions note: output hi-z is defined as the point where data is no longer driven. figure 7. ac measurement i/o waveform table 4. capacitance note: 1. effective capacitance measured with power supply at 5v; sampled only, not 100% tested. 2. at 25c, f = 1mhz. 3. outputs deselected. parameter M41T81 supply voltage (v cc ) 2.0 to 5.5v ambient operating temperature (t a ) C40 to 85c load capacitance (c l ) 100pf input rise and fall times 50ns input pulse voltages 0.2v cc to 0.8 v cc input and output timing ref. voltages 0.3v cc to 0.7 v cc ai02568 0.8v cc 0.2v cc 0.7v cc 0.3v cc symbol parameter (1,2) min max unit c in input capacitance 7 pf c out (3) output capacitance 10 pf t lp low-pass filter input time constant (sda and scl) 50 ns
M41T81 8/29 table 5. dc characteristics note: 1. valid for ambient operating temperature: t a = C40 to 85c; v cc = 2.0 to 5.5v (except where noted). 2. stmicroelectronics recommends the rayovac br1225 or br1632 (or equivalent) as the battery supply. 3. after switchover (v so ), v bat (min) can be 2.0v for crystal with r s = 40k . 4. for rechargeable back-up, v bat (max) may be considered v cc . 5. for irq /ft/out/sqw pin (open drain) table 6. crystal electrical characteristics note: 1. externally supplied if using the so8 package. stmicroelectronics recommends the kds dt-38: 1ta/1tc252e127, tuning fork type (thru-hole) or the dmx-26s: 1tjs125fh2a212, (smd) quartz crystal for industrial temperature operations. kds can be con- tacted at kouhou@kdsj.co.jp or http://www.kdsj.co.jp for further information on this crystal type. 2. load capacitors are integrated within the M41T81. circuit board layout considerations for the 32.768 khz crystal of minimum t race lengths and isolation from rf generating signals should be taken into account. 3. all snaphat ? battery/crystal tops meet these specifications. sym parameter test condition (1) min typ max unit i li input leakage current 0v v in v cc 1 a i lo output leakage current 0v v out v cc 1 a i cc1 supply current switch freq = 400khz 400 a i cc2 supply current (standby) scl,sda = v cc C 0.3v 100 a v il input low voltage C0.3 0.3v cc v v ih input high voltage 0.7v cc v cc + 0.3 v v ol output low voltage i ol = 3.0ma 0.4 v output low voltage (open drain) (5) i ol = 10ma 0.4 v v bat (2 ) battery supply voltage 2.5 (3) 3 3.5 (4) v i bat battery supply current t a = 25c, v cc = 0v oscillator on, v bat = 3v 0.8 1 a sym parameter (1,2,3) min typ max units f o resonant frequency 32.768 khz r s series resistance 60 k c l load capacitance 12.5 pf
9/29 M41T81 operation the M41T81 clock operates as a slave device on the serial bus. access is obtained by implementing a start condition followed by the correct slave ad- dress (d0h). the 20 bytes contained in the device can then be accessed sequentially in the following order: 1. tenths/hundredths of a second register 2. seconds register 3. minutes register 4. century/hours register 5. day register 6. date register 7. month register 8. year register 9. control register 10. watchdog register 11 - 16. alarm registers 17 - 19. reserved 20. square wave register the M41T81 clock continually monitors v cc for an out-of-tolerance condition. should v cc fall below v so , the device terminates an access in progress and resets the device address counter. inputs to the device will not be recognized at this time to prevent erroneous data from being written to the device from a an out-of-tolerance system. the de- vice also automatically switches over to the battery and powers down into an ultra low current mode of operation to conserve battery life. as system pow- er returns and v cc rises above v so , the battery is disconnected, and the power supply is switched to external v cc . for more information on battery storage life refer to application note an1012. 2-wire bus characteristics the bus is intended for communication between different ics. it consists of two lines: a bi-direction- al data signal (sda) and a clock signal (scl). both the sda and scl lines must be connected to a positive supply voltage via a pull-up resistor. the following protocol has been defined: C data transfer may be initiated only when the bus is not busy. C during data transfer, the data line must remain stable whenever the clock line is high. C changes in the data line, while the clock line is high, will be interpreted as control signals. accordingly, the following bus conditions have been defined: bus not busy. both data and clock lines remain high. start data transfer. a change in the state of the data line, from high to low, while the clock is high, defines the start condition. stop data transfer. a change in the state of the data line, from low to high, while the clock is high, defines the stop condition. data valid. the state of the data line represents valid data when after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line may be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated with a stop condition. the number of data bytes transferred between the start and stop conditions is not limited. the information is transmitted byte-wide and each receiver acknowl- edges with a ninth bit. by definition a device that gives out a message is called transmitter, the receiving device that gets the message is called receiver. the device that controls the message is called master. the de- vices that are controlled by the master are called slaves. acknowledge. each byte of eight bits is followed by one acknowledge bit. this acknowledge bit is a low level put on the bus by the receiver whereas the master generates an extra acknowledge relat- ed clock pulse. a slave receiver which is ad- dressed is obliged to generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse in such a way that the sda line is a stable low dur- ing the high period of the acknowledge related clock pulse. of course, setup and hold times must be taken into account. a master receiver must sig- nal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this case the transmitter must leave the data line high to enable the master to generate the stop condition.
M41T81 10/29 figure 8. serial bus data transfer sequence figure 9. acknowledgement sequence ai00587 data clock data line stable data valid start condition change of data allowed stop condition ai00601 data output by receiver data output by transmitter scl from master start clock pulse for acknowledgement 12 89 msb lsb
11/29 M41T81 figure 10. bus timing requirements sequence table 7. ac characteristics note: 1. valid for ambient operating temperature: t a = C40 to 85c; v cc = 2.0 to 5.5v (except where noted). 2. transmitter must internally provide a hold time to bridge the undefined region (300ns max) of the falling edge of scl. sym parameter (1) min typ max units f scl scl clock frequency 0 400 khz t low clock low period 1.3 s t high clock high period 600 ns t r sda and scl rise time 300 ns t f sda and scl fall time 300 ns t hd:sta start condition hold time (after this period the first clock pulse is generated) 600 ns t su:sta start condition setup time (only relevant for a repeated start condition) 600 ns t su:dat (2) data setup time 100 ns t hd:dat data hold time 0 s t su:sto stop condition setup time 600 ns t buf time the bus must be free before a new transmission can start 1.3 s ai00589 sda p tsu:sto tsu:sta thd:sta sr scl tsu:dat tf thd:dat tr thigh tlow thd:sta tbuf s p
M41T81 12/29 read mode in this mode the master reads the M41T81 slave after setting the slave address (see figure 12, page 12). following the write mode control bit (r/w =0) and the acknowledge bit, the word ad- dress 'an' is written to the on-chip address pointer. next the start condition and slave address are repeated followed by the read mode control bit (r/w =1). at this point the master transmitter be- comes the master receiver. the data byte which was addressed will be transmitted and the master receiver will send an acknowledge bit to the slave transmitter. the address pointer is only increment- ed on reception of an acknowledge clock. the M41T81 slave transmitter will now place the data byte at address an+1 on the bus, the master re- ceiver reads and acknowledges the new byte and the address pointer is incremented to an+2. this cycle of reading consecutive addresses will continue until the master receiver sends a stop condition to the slave transmitter. the system-to-user transfer of clock data will be halted whenever the address being read is a clock address (00h to 07h). the update will resume due to a stop condition or when the pointer increments to any non-clock address (08h-13h). note: this is true both in read mode and write mode. an alternate read mode may also be implement- ed whereby the master reads the M41T81 slave without first writing to the (volatile) address point- er. the first address that is read is the last one stored in the pointer (see figure 13, page 13). figure 11. slave address location figure 12. read mode sequence ai00602 r/w slave address start a 01000 11 msb lsb ai00899 bus activity: ack s ack ack ack no ack stop start p sda line bus activity: master r/w data n data n+1 data n+x word address (an) slave address s start r/w slave address ack
13/29 M41T81 figure 13. alternative read mode sequence write mode in this mode the master transmitter transmits to the M41T81 slave receiver. bus protocol is shown in figure 14, page 13. following the start con- dition and slave address, a logic '0' (r/w =0) is placed on the bus and indicates to the addressed device that word address an will follow and is to be written to the on-chip address pointer. the data word to be written to the memory is strobed in next and the internal address pointer is incremented to the next address location on the reception of an acknowledge clock. the M41T81 slave receiver will send an acknowledge clock to the master transmitter after it has received the slave address see figure 11, page 12 and again after it has re- ceived the word address and each data byte. figure 14. write mode sequence ai00895 bus activity: ack s ack ack ack no ack stop start p sda line bus activity: master r/w data n data n+1 data n+x slave address ai00591 bus activity: ack s ack ack ack ack stop start p sda line bus activity: master r/w data n data n+1 data n+x word address (an) slave address
M41T81 14/29 data retention mode with valid v cc applied, the M41T81 can be ac- cessed as described above with read or write cycles. should the supply voltage decay, the pow- er input will be switched from the v cc pin to the battery when v cc falls below the battery back-up switchover voltage (v so ). at this time the clock registers will be maintained by the attached bat- tery supply. as v cc continues to fall, the M41T81 will pass through the register bit reset voltage (v rst ) threshold, not only write protecting itself, but also resetting certain control bits (see table 13, page 21). on power-up, when v cc returns to a nominal value, write protection continues for t rec . for a further, more detailed review of lifetime cal- culations, please see application note an1012. figure 15. power down/up mode ac waveforms table 8. power down/up ac characteristics note: 1. v cc fall time should not exceed 5mv/s. 2. valid for ambient operating temperature: t a = C40 to 85c; v cc = 2.0 to 5.5v (except where noted). table 9. power down/up trip points dc characteristics note: 1. all voltages referenced to v ss . 2. valid for ambient operating temperature: t a = C40 to 85c; v cc = 2.0 to 5.5v (except where noted). symbol parameter (1,2) min typ max unit t pd scl and sda at v ih before power down 0ns t rec scl and sda at v ih after power up 10 s sym parameter (1,2) min typ max unit v so battery back-up switchover voltage v bat C 0.80 v bat C 0.50 v bat C 0.30 v v rst register bit reset voltage 1.1 2.0 v ai00596 v cc trec tpd v so sda scl don't care
15/29 M41T81 clock operation the 20-byte register map (see table 10, page 16) is used to both set the clock and to read the date and time from the clock, in a binary coded decimal format. tenths/hundredths of seconds, seconds, minutes, and hours are contained within the first four registers. note: a write to any clock register will result in the tenths/hundredths of seconds being reset to 00, and tenths/hundredths of seconds cannot be written to any value other than 00. bits d6 and d7 of clock register 03h (century/ hours register) contain the century enable bit (ceb) and the century bit (cb). setting ceb to a '1' will cause cb to toggle, either from '0' to '1' or from '1' to '0' at the turn of the century (de- pending upon its initial state). if ceb is set to a '0,' cb will not toggle. bits d0 through d2 of register 04h contain the day (day of week). registers 05h, 06h, and 07h contain the date (day of month), month and years. the ninth clock register is the control register (this is described in the clock calibration section). bit d7 of register 01h con- tains the stop bit (st). setting this bit to a '1' will cause the oscillator to stop. if the device is expect- ed to spend a significant amount of time on the shelf, the oscillator may be stopped to reduce cur- rent drain. when reset to a '0' the oscillator restarts within one second. the eight clock registers may be read one byte at a time, or in a sequential block. the control reg- ister (address location 08h) may be accessed in- dependently. provision has been made to assure that a clock update does not occur while any of the eight clock addresses are being read. if a clock ad- dress is being read, an update of the clock regis- ters will be halted. this will prevent a transition of data during the read. note: when a power failure occurs, the ht bit will automatically be set to a '1.' this will prevent the clock from updating the tim ekeeper ? registers, and will allow the user to read the exact time of the power-down event. resetting the ht bit to a '0' will allow the clock to update the timekeeper regis- ters with the current time. timekeeper ? registers the M41T81 offers 20 internal registers which contain clock, alarm, watchdog, flag, square wave and control data. these registers are mem- ory locations which contain external (user accessi- ble) and internal copies of the data (usually referred to as biport ? timekeeper cells). the external copies are independent of internal func- tions except that they are updated periodically by the simultaneous transfer of the incremented inter- nal copy. the internal divider (or clock) chain will be reset upon the completion of a write to any clock address. the system-to-user transfer of clock data will be halted whenever the address being read is a clock address (00h to 07h). the update will resume ei- ther due to a stop condition or when the pointer increments to any non-clock address (08h-13h). timekeeper and alarm registers store data in bcd. control, watchdog and square wave reg- isters store data in binary format.
M41T81 16/29 table 10. timekeeper ? register map keys: s = sign bit ft = frequency test bit st = stop bit 0 = must be set to '0' bmb0-bmb4 = watchdog multiplier bits ceb = century enable bit cb = century bit out = output level abe = alarm in battery back-up mode enable bit afe = alarm flag enable flag rb0-rb1 = watchdog resolution bits rpt1-rpt5 = alarm repeat mode bits wdf = watchdog flag (read only) af = alarm flag (read only) sqwe = square wave enable rs0-rs3 = sqw frequency ht = halt update bit addr function/range bcd format d7 d6 d5 d4 d3 d2 d1 d0 00h 0.1 seconds 0.01 seconds seconds 00-99 01h st 10 seconds seconds seconds 00-59 02h 0 10 minutes minutes minutes 00-59 03h ceb cb 10 hours hours (24 hour format) century/ hours 0-1/00-23 04h 0 0 0 0 0 day of week day 01-7 05h 0 0 10 date date: day of month date 01-31 06h 0 0 0 10m month month 01-12 07h 10 years year year 00-99 08h out ft s calibration control 09h 0 bmb4 bmb3 bmb2 bmb1 bmb0 rb1 rb0 watchdog 0ah afe sqwe abe al 10m alarm month al month 01-12 0bh rpt4 rpt5 ai 10 date alarm date al date 01-31 0ch rpt3 ht ai 10 hour alarm hour al hour 00-23 0dh rpt2 alarm 10 minutes alarm minutes al min 00-59 0eh rpt1 alarm 10 seconds alarm seconds al sec 00-59 0fhwdfaf000000 flags 10h00000000 reserved 11h00000000 reserved 12h00000000 reserved 13hrs3rs2rs1rs00000sqw
17/29 M41T81 calibrating the clock the M41T81 is driven by a quartz controlled oscil- lator with a nominal frequency of 32,768 hz. the devices are tested not exceed +/C35 ppm (parts per million) oscillator frequency error at 25 o c, which equates to about +/C1.53 minutes per month (see figure 18, page 22). when the cali- bration circuit is properly employed, accuracy im- proves to better than +1/C2 ppm at 25c. the oscillation rate of crystals changes with tem- perature. the M41T81 design employs periodic counter correction. the calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as shown in figure 19, page 22. the number of times pulses which are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five calibration bits found in the control register. adding counts speeds the clock up, subtracting counts slows the clock down. the calibration bits occupy the five lower order bits (d4-d0) in the control register 08h. these bits can be set to represent any value between 0 and 31 in binary form. bit d5 is a sign bit; '1' indi- cates positive calibration, '0' indicates negative calibration. calibration occurs within a 64 minute cycle. the first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. if a bi- nary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or C2.034 ppm of adjustment per calibra- tion step in the calibration register. assuming that the oscillator is running at exactly 32,768 hz, each of the 31 increments in the calibration byte would represent +10.7 or C5.35 seconds per month which corresponds to a total range of +5.5 or C2.75 minutes per month. two methods are available for ascertaining how much calibration a given M41T81 may require. the first involves setting the clock, letting it run for a month and comparing it to a known accurate ref- erence and recording deviation over a fixed period of time. calibration values, including the number of seconds lost or gained in a given period, can be found in application note an934, timekeep- er ? calibration. this allows the designer to give the end user the ability to calibrate the clock as the environment requires, even if the final prod- uct is packaged in a non-user serviceable enclo- sure. the designer could provide a simple utility that accesses the calibration byte. the second approach is better suited to a manu- facturing environment, and involves the use of the irq /ft/out/sqw pin. the pin will toggle at 512hz, when the stop bit (st, d7 of 01h) is '0,' the frequency test bit (ft, d6 of 08h) is '1,' the alarm flag enable bit (afe, d7 of 0ah) is '0,' and the square wave enable bit (sqwe, d6 of 0ah) is '0' and the watchdog register (09h = 0) is reset. any deviation from 512 hz indicates the degree and direction of oscillator frequency shift at the test temperature. for example, a reading of 512.010124 hz would indicate a +20 ppm oscilla- tor frequency error, requiring a C10 (xx001010) to be loaded into the calibration byte for correction. note that setting or changing the calibration byte does not affect the frequency test output fre- quency. the irq /ft/out/sqw pin is an open drain output which requires a pull-up resistor to v cc for proper operation. a 500-10k resistor is recommended in order to control the rise time. the ft bit is cleared on power-down.
M41T81 18/29 setting alarm clock registers address locations 0ah-0eh contain the alarm set- tings. the alarm can be configured to go off at a prescribed time on a specific month, date, hour, minute, or second or repeat every year, month, day, hour, minute, or second. it can also be pro- grammed to go off while the M41T81 is in the bat- tery back-up mode to serve as a system wake-up call. bits rpt5-rpt1 put the alarm in the repeat mode of operation. table 11, page 19 shows the possi- ble configurations. codes not listed in the table de- fault to the once per second mode to quickly alert the user of an incorrect alarm setting. when the clock information matches the alarm clock settings based on the match criteria defined by rpt5-rpt1, the af (alarm flag) is set. if afe (alarm flag enable) is also set (and sqwe is '0.'), the alarm condition activates the irq /ft/out/ sqw pin. note: if the address pointer is allowed to incre- ment to the flag register address, an alarm con- dition will not cause the interrupt/flag to occur until the address pointer is moved to a different ad- dress. it should also be noted that if the last ad- dress written is the alarm seconds, the address pointer will increment to the flag address, causing this situation to occur. the irq /ft/out/sqw output is cleared by a read to the flags register as shown in figure 16. a subsequent read of the flags register is necessary to see that the value of the alarm flag has been reset to '0.' the irq/ft/out/sqw pin can also be activated in the battery back-up mode. the irq/ft/out/ sqw will go low if an alarm occurs and both abe (alarm in battery back-up mode enable) and afe are set. figure 17 illustrates the back-up mode alarm timing. figure 16. alarm interrupt reset waveform figure 17. back-up mode alarm waveform irq/ft/out/sqw active flag 0fh 0eh 10h high-z ai04617 v cc irq/ft/out/sqw abe and afe bits af bit in flags register high-z v so high-z trec ai05663
19/29 M41T81 table 11. alarm repeat modes watchdog timer the watchdog timer can be used to detect an out- of-control microprocessor. the user programs the watchdog timer by setting the desired amount of time-out into the watchdog register, address 09h. bits bmb4-bmb0 store a binary multiplier and the two lower order bits rb1-rb0 select the resolu- tion, where 00 = 1/16 second, 01 = 1/4 second, 10 = 1 second, and 11 = 4 seconds. the amount of time-out is then determined to be the multiplica- tion of the five-bit multiplier value with the resolu- tion. (for example: writing 00001110 in the watchdog register = 3*1, or 3 seconds). if the processor does not reset the timer within the spec- ified period, the M41T81 sets the wdf (watchdog flag) and generates a watchdog interrupt. the watchdog timer can be reset by having the mi- croprocessor perform a write of the watchdog register. the time-out period then starts over. should the watchdog timer time-out, a value of 00h needs to be written to the watchdog register in order to clear the irq /ft/out/sqw pin. this will also disable the watchdog function until it is again programmed correctly. a read of the flags register will reset the watchdog flag (bit d7; register 0fh). the watchdog function is automatically disabled upon power-up and the watchdog register is cleared. if the watchdog function is set, the fre- quency test function is activated, and the sqwe bit is '0,' the watchdog function prevails and the frequency test function is denied. rpt5 rpt4 rpt3 rpt2 rpt1 alarm setting 1 1 1 1 1 once per second 1 1 1 1 0 once per minute 1 1 1 0 0 once per hour 1 1 0 0 0 once per day 1 0 0 0 0 once per month 0 0 0 0 0 once per year
M41T81 20/29 square wave output the M41T81 offers the user a programmable square wave function which is output on the sqw pin. rs3-rs0 bits located in 13h establish the square wave output frequency. these frequencies are listed in table 12. once the selection of the sqw frequency has been completed, the irq /ft/ out/sqw pin can be turned on and off under soft- ware control with the square wave enable bit (sqwe) located in register 0ah. table 12. square wave output frequency square wave bits square wave rs3 rs2 rs1 rs0 frequency units 0000none- 0 0 0 1 32.768 khz 0 0 1 0 8.192 khz 0 0 1 1 4.096 khz 0 1 0 0 2.048 khz 0 1 0 1 1.024 khz 0110512hz 0111256hz 1000128hz 100164hz 101032hz 101116hz 11008hz 11014hz 11102hz 11111hz
21/29 M41T81 century bit bits d7 and d6 of clock register 03h contain the century enable bit (ceb) and the century bit (cb). setting ceb to a '1' will cause cb to tog- gle, either from a '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). if ceb is set to a '0,' cb will not toggle. output driver pin when the ft bit, afe bit, sqwe bit, and watch- dog register are not set, the irq /ft/out/sqw pin becomes an output driver that reflects the con- tents of d7 of the control register. in other words, when d7 (out bit) and d6 (ft bit) of address lo- cation 08h are a '0,' then the irq /ft/out/sqw pin will be driven low. note: the irq /ft/out/sqw pin is an open drain which requires an external pull-up resistor. preferred initial power-on default upon initial application of power to the device, the following register bits are set to a '0' state: watch- dog register; afe; abe; sqwe; and ft. the fol- lowing bits are set to a '1' state: st; out; and ht (see table 13, page 21). table 13. preferred default values note: 1. bmb0-bmb4, rb0, rb1. 2. state of other control bits undefined. 3. uc = unchanged condition st ht out ft afe sqwe abe watchdog register (1) initial power-up (2) 1110000 0 subsequent power-up (with battery back-up) (3) uc 1 uc 0 uc uc uc 0
M41T81 22/29 figure 18. crystal accuracy across temperature figure 19. clock calibration ai00999 C160 0 10203040506070 frequency (ppm) temperature c 80 C10 C20 C30 C40 C100 C120 C140 C40 C60 C80 20 0 C20 ? f = -0.038 (t - t 0 ) 2 10% f ppm c 2 t 0 = 25 c ai00594b normal positive calibration negative calibration
23/29 M41T81 part numbering table 14. ordering information scheme note: 1. the 28-pin soic package (soh28) requires the battery/crystal package (e.g., snaphat ? ) which is ordered separately under the part number m4txx-br12shx in plastic tube or m4txx-br12shxtr in tape & reel form. 2. contact local sales office caution: do not place the snaphat battery package m4txx-br12sh in conductive foam as it will drain the lithium button-cell battery. for a list of available options (e.g., speed, package) or for further information on any aspect of this device, please contact the st sales office nearest to you. table 15. snaphat battery/crystal table example: m41t 81 mh 6 tr device type m41t supply voltage and write protect voltage 81 = v cc = 2.0 to 5.5v package m = so8 mh (1,2) = soh28 temperature range 6 = C40c to 85c shipping method for soic blank = tubes tr = tape & reel part number description package m4t28-br12sh lithium battery (48mah)/crystal snaphat sh m4t32-br12sh lithium battery (120mah)/crystal snaphat sh
M41T81 24/29 package mechanical information figure 20. so8 C 8-lead plastic small package outline note: drawing is not to scale. table 16. so8 C 8-lead plastic small outline (150 mils body width), package mechanical data symb mm inches typ min max typ min max a 1.35 1.75 0.053 0.069 a1 0.10 0.25 0.004 0.010 b 0.33 0.51 0.013 0.020 c 0.19 0.25 0.007 0.010 d 4.80 5.00 0.189 0.197 e 3.80 4.00 0.150 0.157 e 1.27 C C 0.050 C C h 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 l 0.40 0.90 0.016 0.035 0 8 0 8 n8 8 cp 0.10 0.004 so-b e n cp b e a2 d c l a1 h a 1
25/29 M41T81 figure 21. soh28 C 28-lead plastic small package outline note: drawing is not to scale. table 17. soh28 C 28-lead plastic small outline, package mechanical data symb mm inches typ min max typ min max a 3.05 0.120 a1 0.05 0.36 0.002 0.014 a2 2.34 2.69 0.092 0.106 b 0.36 0.51 0.014 0.020 c 0.15 0.32 0.006 0.012 d 17.71 18.49 0.697 0.728 e 8.23 8.89 0.324 0.350 e 1.27 C C 0.050 C C eb 3.20 3.61 0.126 0.142 h 11.51 12.70 0.453 0.500 l 0.41 1.27 0.016 0.050 a 08 08 n2828 cp 0.10 0.004 soh-b e n d c l a1 1 h a cp be a2 eb
M41T81 26/29 figure 22. sh C 4-pin snaphat housing for 48mah battery and crystal, package outline note: drawing is not to scale. table 18. sh C 4-pin snaphat housing for 48mah battery and crystal, package mechanical data symb mm inches typ min max typ min max a 9.78 0 0.385 a1 6.73 7.24 0.265 0.285 a2 6.48 6.99 0.255 0.275 a3 0.38 0 0.015 b 0.46 0.56 0.018 0.022 d 21.21 21.84 0.835 0.860 e 14.22 14.99 0.560 0.590 ea 15.55 15.95 .6122 .6280 eb 3.20 3.61 0.126 0.142 l 2.03 2.29 0.080 0.090 shtk-a a1 a d e ea eb a2 b l a3
27/29 M41T81 figure 23. sh C 4-pin snaphat housing for 120mah battery and crystal, package outline note: drawing is not to scale. table 19. sh C 4-pin snaphat housing for 120mah battery and crystal, package mechanical data symb mm inches typ min max typ min max a 10.54 0 0.415 a1 8.00 8.51 0.315 0.335 a2 7.24 8.00 0.285 0.315 a3 0.38 0 0.015 b 0.46 0.56 0.018 0.022 d 21.21 21.84 0.835 0.860 e 17.27 18.03 0.680 0.710 ea 15.55 15.95 .6122 .6280 eb 3.20 3.61 0.126 0.142 l 2.03 2.29 0.080 0.090 shtk-a a1 a d e ea eb a2 b l a3
M41T81 28/29 revision history table 20. document revision history date rev. # revision details december 2001 1.0 first issue 01/21/02 1.1 fix table footnotes (table 5, 6) 05/01/02 1.2 modify reflow time and temperature footnote (table 2) 06/05/02 1.3 modify data retention text, trip points (table 9) 06/10/02 1.4 corrected supply voltage values (table 2, 3) 07/03/02 1.5 modify dc characteristics, crystal electrical table footnotes, preferred default values (table 5, 6, 13) 10/11/02 1.6 add marketing status (figure 2; table 14); adjust footnotes (figure 4; table 5)
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up, backup, backup, backup, backup, backup, backup, backup, backup, backup, backup, backup, backup, backup, backup, backup, wri te protect, write protect, write protect, write protect, write protect, write protect, write protect, write protect, write protect, write protect, write protect , write protect, write protect, write protect, write protect, write protect, write protect, write protect, write protect, write protect, write protect, write protect, write p rotect, write protect, write protect, industrial, industrial, industrial, industrial, industrial, industrial, industrial, industrial, industrial, industrial, industrial, vindust rial, industrial, industrial, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, soic, soic, soic, soic, soic, soic, soic, soic, soic, soic, soic, soic, soic, soic , soic information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners. ? 2002 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - 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